1. Field of the Invention
The invention relates to a semiconductor memory device and a method of fabricating the same, and more particularly to a semiconductor memory device storing data by accumulating electric charges in a capacitor formed in the device, and a method of fabricating the same.
2. Description of the Related Art
A dynamic random access memory (DRAM) is one of memories comprises of a transistor and a capacitor. FIGS. 1A to 1E are cross-sectional view of a cell in a conventional dynamic random access memory, each illustrating a step of a method of fabricating the same.
First, as illustrated in FIG. 1A, isolating regions 2 are formed at a surface of a semiconductor substrate 1 by the shallow trench isolation (STI) process. The adjacent isolation regions 2 define a region therebetween in which a transistor is to be fabricated.
Then, transistors (not illustrated) are fabricated between the isolation regions 2, followed by ion-implantation to the semiconductor substrate 1 between the isolation regions 2 to thereby form diffusion layers 3 at a surface of the semiconductor substrate 1.
Then, a first interlayer insulating film 4 is formed on the semiconductor substrate 1. After planarization of the first interlayer insulating film 4 by chemical mechanical polishing (CMP), a photoresist film (not illustrated) is deposited on the first interlayer insulating film 4. After patterning the photoresist film, the first interlayer insulating film 4 is etched with the patterned photoresist film being used as a mask, to thereby form contact holes 5 throughout the first interlayer insulating film 4 such that the contact holes 5 reach the diffusion layer 3.
Then, polysilicon is grown entirely over the first interlayer insulating film 4 and the diffusion layer 3, and thereafter, is etched back by dry etching. As a result, the polysilicon remains non-etched only in the contact holes 5. The polysilicon remaining in the contact holes 5 defines first electrically conductive layers 6 acting as pads.
Then, as illustrated in FIG. 1B, an interlayer insulating film 7 is formed entirely over the second interlayer insulating film 4 and the first electrically conductive layers 6. Then, there are formed contact holes (not illustrated) through both the interlayer insulating film 7 and the first interlayer insulating film 4 such that the contact holes connect later mentioned bit lines to a circuit (not illustrated) formed on the semiconductor substrate 1.
Then, a tungsten polycide film is formed on the interlayer insulating film 7. Then, the tungsten polycide film is patterned by photolithography and etching to thereby form bit lines 8 on the interlayer insulating film 7.
Then, as illustrated in FIG. 1C, a second interlayer insulating film 9 is formed on the interlayer insulating film such that the bit line 8 are entirely covered with the second interlayer insulating film 9. After planarizing the second interlayer insulating film 9, contact holes 10 are formed throughout the second interlayer insulating film 9 by photolithography and etching such that the contact holes 10 reach the first electrically conductive layers 6.
Then, the contact holes 10 are filled with polysilicon to thereby form plugs 11 in the contact holes 10 in the same manner as forming the first electrically conductive layers 6.
Then, as illustrated in FIG. 1D, a third interlayer insulating film 12 is formed entirely over the second interlayer insulating film 9 and the plugs 11. Then, the third interlayer insulating film 12 is patterned by photolithography and etching to thereby form recesses 13 throughout the third interlayer insulating film 12 such that the recesses 13 reach the plugs 11.
Then, as illustrated in FIG. 1E, each of the recesses 13 is covered at its inner sidewall and bottom with a lower electrode 14 composed of polysilicon.
It is preferable for a capacitor to have a greater capacity for writing data thereinto or reading data therefrom. In order to enhance a capacity of a capacitor, each of the recesses 13 illustrated in FIG. 1E needs to have a greater surface area, that is, the lower electrode 14 needs to have a greater height. To this end, the third interlayer insulating film 12 needs to have a greater thickness.
However, if the third interlayer insulating film 12 is designed to have a greater thickness, the contact holes 5, 10 and 13 reaching the circuit formed on the semiconductor substrate 1 have to have a greater depth, resulting in an increase in difficulty for fabricating the semiconductor memory device.
A memory used in a computer has been designed to have a greater capacity, and a cell in a semiconductor memory device has been designed to be fabricated in a smaller size. Accordingly, there is caused a problem that it is more and more difficult to stably pattern a photoresist film for forming the contact holes 10 in accordance with a minimum design rule.
For instance, Japanese Patent No. 2850833 (Japanese Unexamined Patent Publication No. 9-232427) has suggested a method of fabricating a semiconductor device, including the steps of forming a plurality of wirings on a semiconductor substrate, forming a sidewall layer around each of sidewalls of the wirings, forming an interlayer insulating film covering the wirings and the sidewall layers therewith, and etching both the interlayer insulating layer and the sidewall layers by making an etching rate of the sidewall layers equal to or greater than an etching rate of the interlayer insulating film, to thereby form contact holes between the wirings. Each of the sidewall layers is comprised of a silicon dioxide film into which impurity is doped, and a coat insulating film keeping the silicon dioxide film away from the semiconductor substrate by covering both sidewalls of the wirings and the semiconductor substrate therewith.
Japanese Unexamined Patent Publication No. 9-97902 has suggested a method of fabricating a semiconductor device, including the steps of forming a first wiring layer on a semiconductor substrate, a forming a first etching stopper film covering the first wiring layer therewith, forming a first interlayer insulating film over the first etching stopper film and the semiconductor substrate, forming a second wiring layer on the first interlayer insulating film, forming a second etching stopper film on the second wiring layer such that the second etching stopper film is horizontally more extensive than the second wiring layer and projects from a sidewall of the second wiring layer, forming a second interlayer insulating film on the semiconductor substrate, and forming a contact hole extending from a surface of the second interlayer insulating film to either a surface of the first etching stopper film or a surface of the semiconductor substrate. An etching mask formed on the second interlayer insulating film is composed of the same material as a material of which the second etching stopper film is composed.
Japanese Unexamined Patent Publication No. 9-321024 has suggested a method of fabricating a semiconductor device, including the steps of etching a silicon dioxide film relative to a silicon nitride film through the use of a first process gas containing phlorocarbon gas having no hydrogen bondings, and etching the silicon dioxide film relative to the silicon nitride film through the use of a second process gas containing CO gas and phlorocarbon gas having hydrogen bondings.
Japanese Unexamined Patent Publication No. 11-87653 has suggested a method of fabricating a semiconductor device, including the steps of forming a gate insulating film in active regions on a semiconductor substrate, forming a plurality of first gate electrodes in a first region and a plurality of second gate electrodes in a second region, the first gate electrodes having a high patterning density and the second gate electrodes having a low patterning density, forming source and drain regions in the semiconductor substrate around each of the first and second gate electrodes, forming a first insulating film on the semiconductor substrate so that the first insulating film covers the first and second gate electrodes therewith, forming a second insulating film on the first insulating film, the second insulating film having different etching characteristic from that of the first insulating film, forming an interlayer insulating film on the semiconductor substrate so that the interlayer insulating film covers the second insulating film in the first region and the second gate electrodes in the second region therewith, the interlayer insulating film having different etching characteristic from that of the second insulating film, and forming a hole in a self-aligning manner in the first region by using the second insulating film as an etching stopper, the hole extending throughout the interlayer insulating film and the first insulating film, making contact with the first insulating film, and reaching one of the source and drain regions.
Japanese Unexamined Patent Publication No. 11-16886 has suggested a method of etching a silicon dioxide film exposed through openings of a resist mask formed on a semiconductor substrate, through the use of a gas containing fluorocarbon gas and alcohol.
The above-mentioned problems remain unsolved even in the above-mentioned Publications.
It is an object of the present invention to provide a semiconductor memory device which is capable of increasing a capacity of a capacitor without deepening a contact hole reaching a peripheral circuit, and forming a recess defining a capacitor, in a self-aligning manner not in accordance with a minimum design rule.
It is also an object of the present invention to provide a method of fabricating such a semiconductor memory device.
In one aspect of the present invention, there is provided a semiconductor memory device including (a) a semiconductor substrate on which a circuit is formed, (b) a first interlayer insulating film formed on the semiconductor substrate, (c) a plurality of bit lines formed on the first interlayer insulating film, a contact hole being formed through the first interlayer insulating film between adjacent bit lines such that the contact hole reaches the semiconductor substrate, (d) a second interlayer insulating film formed on the first interlayer insulating film such that the second interlayer insulating film covers the bit lines therewith, (e) a first electrically conductive layer buried in the contact hole, a recess being formed through the second interlayer insulating film between adjacent bit lines such that the recess reaches the first electrically conductive layer, and (f) a second electrically conductive layer covering a bottom and an inner sidewall of the recess therewith such that the second electrically conductive layer is electrically isolated from the bit lines.
In the conventional semiconductor memory device, a recess for defining a capacitor is formed only above bit lines. In contrast, in accordance with the present invention, the recess for defining a capacitor is formed not only above bit lines but also at the side of bit lines. Hence, it is possible to increase a capacity of a capacitor without an increase in a thickness of an interlayer insulating film in which a recess for defining a capacitor is to be formed.
It is preferable that the semiconductor memory device further includes an insulating film covering upper and side surfaces of the bit lines therewith. The insulating film formed around a first bit line and the insulating film formed around a second bit line adjacent to the first bit line both partially defines a part of the inner sidewall of the recess, the bottom of the recess being extensive between the insulating films.
In accordance with this arrangement, the recess can be formed not in accordance with a minimum design rule but in a self-aligning manner by etching the second interlayer insulating film with the insulating film being used as an etching stopper, ensuring reduction in the number of fabrication steps.
It is preferable that the insulating film is composed of silicon nitride, and the second interlayer insulating film is composed of silicon dioxide.
A film composed of silicon dioxide has a dielectric constant about half of a dielectric constant of a film composed of a silicon nitride. For instance, a silicon nitride film has a dielectric constant of 7.5, whereas a silicon dioxide film has a dielectric constant of 3.9. Thus, a combination of a silicon nitride film and a silicon dioxide film would reduce a capacity of a bit line. The capacity defined between the bit line and the second electrically conductive layer is greatest.
In other words, in accordance with the present invention, since the recess is formed reaching a layer on which the bit lines are formed, it would be possible to increase a capacity of a capacitor, even if an interlayer insulating film in which the recess is to be formed did not have an increased thickness.
It is preferable that the semiconductor memory device further includes a second insulating film sandwiched between each of the bit lines and the insulating film, in which case, it is preferable that the insulating film is composed of silicon nitride, the second interlayer insulating film is composed of silicon dioxide, and the second insulating film is composed of silicon dioxide.
It is preferable that the semiconductor memory device further includes a third interlayer insulating film sandwiched between the first and second interlayer insulating films, the bit lines being formed on the third interlayer insulating film, the recess being formed through the second and third interlayer insulating films between adjacent bit lines such that the recess reaches the first electrically conductive layer.
For instance, the third interlayer insulating film is composed of silicon dioxide.
There is further provided a semiconductor memory device including (a) a semiconductor substrate on which a circuit is formed, (b) a first interlayer insulating film formed on the semiconductor substrate, (c) a plurality of bit lines formed on the first interlayer insulating film, a contact hole being formed through the first interlayer insulating film between adjacent bit lines such that the contact hole reaches the semiconductor substrate, (d) a first insulating film covering an upper surface of each of the bit lines therewith, (e) a second interlayer insulating film formed on the first interlayer insulating film such that the second interlayer insulating film covers both the first insulating film and the bit lines therewith, (e) a first electrically conductive layer buried in the contact hole, a recess being formed through the second interlayer insulating film between adjacent bit lines such that the recess reaches the first electrically conductive layer, (f) a second insulating film formed on an inner sidewall of the recess, and (g) a second electrically conductive layer formed on the second insulating film and covering a bottom of the recess therewith.
In another aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, including the steps of (a) forming a first interlayer insulating film on a semiconductor substrate, (b) forming a plurality of contact holes through the first interlayer insulating film, (c) forming a first electrically conductive layer in each of the contact holes, (d) forming a pattern of a wiring layer on the first interlayer insulating film such that the wiring layer is located between the contact holes when viewed from above, (e) covering the wiring layer at its upper and side surfaces with an etching stopper film, (f) forming a second interlayer insulating film on the first interlayer insulating film such that the second interlayer insulating film covers the etching stopper film therewith, (g) forming a recess through the second interlayer insulating film such that the etching stopper film formed around a first wiring layer and the etching stopper film formed around a second wiring layer adjacent to the first wiring layer are both exposed to the recess and that the recess reaches the first electrically conductive layer, and (h) forming a second electrically conductive layer such that the recess is covered at its inner sidewall and a bottom with the second electrically conductive layer.
It is preferable that the etching stopper film is composed of silicon nitride, and the second interlayer insulating film is composed of silicon dioxide.
It is preferable that the method further includes the step (i) of forming an insulating film on the wiring layer, the step (i) being carried out between the steps (d) and (e).
It is preferable that the insulating film is composed of silicon dioxide.
It is preferable that the method further includes the step (j) of forming a third interlayer insulating film on the first interlayer insulating film, the step (j) being carried out between the steps (c) and (d), the wiring layer being formed on the third interlayer insulating film.
There is further provided a method of fabricating a semiconductor memory device, including the steps of (a) forming a first interlayer insulating film on a semiconductor substrate, (b) forming a plurality of contact holes through the first interlayer insulating film, (c) forming a first electrically conductive layer in each of the contact holes, (d) forming a pattern of a wiring layer on the first interlayer insulating film such that the wiring layer is located between the contact holes when viewed from above, (e) covering the wiring layer at its upper surface with a first insulating film, (f) forming a second interlayer insulating film such that the second interlayer insulating film covers the first insulating film and the wiring layer therewith, (g) forming a recess through the second interlayer insulating film such that the first insulating film formed around a first wiring layer and the first insulating film formed around a second wiring layer adjacent to the first wiring layer are both exposed to the recess and that the recess reaches the first electrically conductive layer, (h) covering the recess at its inner sidewall with a second insulating film, and (i) forming a second electrically conductive layer such that the second insulating film and a bottom of the recess are covered with the second electrically conductive layer.
It is preferable that the first insulating film is composed of silicon nitride, the second interlayer insulating film is composed of silicon dioxide, and the second insulating film is composed of silicon dioxide.
The advantages obtained by the aforementioned present invention will be described hereinbelow.
In accordance with the present invention, the recess for defining a capacitor is formed throughout the second interlayer insulating film and reaches the first electrically conductive film. As a result, the recess is formed not only above the bit lines but also at the side of the bit lines. Hence, it is possible to increase a capacity of a capacitor without an increase in a thickness of an interlayer insulating film in which the recess is to be formed.
The etching stopper film formed around a first bit line and the etching stopper film formed around a second bit line located adjacent to the first bit line can be exposed to the recess by covering the bit lines with the etching stopper film, forming the second interlayer insulating film so that the etching stopper film is covered with the second interlayer insulating film, and etching the second interlayer insulating film. Thus, the recess can be formed not in accordance with a minimum design rule but in a self-aligning manner, ensuring reduction in the number of fabrication steps.
In addition, it would be possible to reduce a capacity of the bit lines by using a silicon dioxide film together with the etching stopper film composed of silicon nitride, or by partially replacing the silicon nitride film with a silicon dioxide film, because silicon dioxide has a smaller dielectric constant than that of silicon nitride.
Thus, the present invention makes it possible to increase a capacity of a capacitor without deepening a contact hole reaching a peripheral circuit. In addition, it is possible to reduce the number of fabrication steps, since the recess can be formed in a self-aligning manner.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.